1. Field of the Invention
The invention relates generally to the field of integrated circuits comprising transistor switches connected in complementary metal-oxide-semiconductor (CMOS) and more specifically to current steering CMOS switching circuits.
2. Description of the Prior Art
Emitter-coupled logic (ECL) switching circuits have been used for a number of years in applications requiring very high speed switching. In ECL switching circuits, two bipolar transistors form the basic switch. The emitters of the transistors are connected together and are further connected to a current source. The transistors' collectors are connected through load resistors to a voltage source. The bases of the transistors are controlled by differential input signals (or, alternatively, the base of one transistor is controlled by a single input signal and the base of the other transistor is controlled by a reference voltage). The signal outputs are taken from the nodes between the load resistors and the transistor collectors.
In non-ECL switching circuits, such as conventional resistor-transistor or transistor-transistor logic switching circuits, the switching transistors switch between an on, or conducting, condition and an off, or non-conducting, condition. When the single input signal forces the switch transistor to switch from the off condition to the on condition, the transistor takes a relatively long period of time to perform the switch since parasitic capacitances in the transistor must be charged. ECL circuits reduce this lengthy turn-on period by having both transistors comprising the switch biased to remain on at all times. In ECL, the swings in the voltage levels of the logic input signals cause swings in the voltage levels of the logic output signals, but such output signals always remain at non-zero voltage levels. Since the transistors forming the switch are never turned off, the parasitic capacitances are always charged and so the switch can perform logic operations very rapidly.
ECL circuits use bipolar transistor technology, which is expensive to implement compared to metal oxide semiconductor (MOS) technology that is used in many digital integrated circuits. In addition, ECL circuits require large amounts of power to operate. However, a MOS analog to ECL logic has recently been developed in the form of current-steering logic, in which the source terminals of a pair of MOS transistors are connected together to form a node, which is further connected to a current source. The digital input signals are applied to the gate terminals of the MOS transistors, and the drain terminals are connected to a voltage source. Instead of the output signal being a change in voltage level at the output terminal, which may be the drain terminals, the output signal is taken as a change in the current directed to the output terminals; the transistors steer the current to one output terminal or the other depending on the conditions of the signals at the respective transistors' gate terminals.
Recently, CMOS technology has become popular as a way of reducing the power dissipation from that of conventional MOS circuits using P-channel or N-channel transistors exclusively. In CMOS technology, transistors are typically used in pairs. One transistor in a pair may have a P-channel and the other an N-channel, the two transistors being connected in series between a voltage source and ground with the output being taken from the node between them. If the transistors are both driven by the same logic signal, one will be on and the other off. If the transistor connected to ground is on, the voltage level of the output signal will be near ground, but if the transistor connected to the voltage source is on, the voltage level of the output signal will be near that of the voltage source.
The CMOS technology uses more space on a chip, but it significantly reduces the power dissipation of the circuit as compared to other technologies. Since only one transistor in each pair is on at one time, little current flows except when the transistors are switching. Thus power is dissipated primarily only when the transistors are switching between the on and off conditions.
As is apparent, typical CMOS circuits are voltage-sensitive, that is, logic levels are defined by voltages at the output node. However, turning the transistors on and off requires currents to flow into and out of the internal parasitic capacitances that are in both transistors in the pair, which lengthens the time required to perform the switching operation. Thus, conventional CMOS switches are much slower than ECL switches.